This invention relates generally to processing within a computing environment, and more particularly to switch failover control in a multi-processor computer system.
Today's computing platforms and processing system are moving toward an I/O interconnect topology that provides a single communication path between each peripheral device and the host. These computing platforms and processing systems may use packetized communications within the tree structure. Examples of such computing platforms and processing systems include what is referred to as, for example, peripheral component interconnect (PCI) systems and PCI Express (PCIe) systems. Peripheral devices are discovered by such platforms and systems through an enumeration process performed by a host system element.
I/O adapters or peripheral devices are connected to a primary processor node and to a secondary failover processor node through its I/O expansion network consisting of pairs of interconnected proprietary PCIe fan-output chips (i.e., switches), which can be costly.